TRAVEO T2G CYT4DN · 1280×480 @ 60 Hz

OTF and LBO layer timing over SMIF

A fullscreen sprite animation split into three side-by-side layers: OTF left, LBO middle, OTF right. The display scans frame K while the CPU and blit engine prepare frame K+1. Change the HyperRAM and flash settings to see when the OTF line buffers underrun and when the middle layer falls out of step with the sides.

SMIF bus

SMIF clock (MHz)

Burst size (bytes)

HyperRAM

Initial latency (clk)

Fixed 2× latency

Flash (HyperFlash / Octal)

Initial latency (clk)

Where the images live

OTF sources in

LBO frames in

Layers and content

Pixel format

OTF line buffer (lines)

Heavy band cost, lines 150–299

Frame switch

Commit mode

HyperRAM effective

per channel

Flash effective

per channel

OTF need per layer

normal lines

LBO render time

OTF glitched lines

over 3 refreshes

Layers in sync

LBO vs OTF frame

Live scan, three refreshes

Speed

Frame K Frame K+1 OTF lines ready in the ring Underrun line Scan line

How the model works

Effective bandwidth for each memory comes from the SMIF clock, burst size and initial latency:

MB/s = clock × burst ÷ (5 + latency + burst ÷ 2)

HyperRAM and flash are on separate SMIF channels. Sources in the same memory share one channel.
While the LBO render shares a channel with the OTF layers, bandwidth splits evenly among the OTF writers that have room in their ring and the LBO render. Unused share goes to the LBO render.
Each OTF writer restarts at line 0 at the frame trigger (start of vertical blanking) and stays at most one line buffer ahead of the scan.
The CPU commits K+1 at 55% of refresh 1. The LBO render of K+1 starts at 40%.
Display timing: 1560 × 525 total, 49 MHz pixel clock, 31.7 µs per line. Each layer is about 427 px wide.

Things to try

Start with the defaults: all in flash at 166 MHz with 64-byte bursts. No glitches, layers in sync.
Set the clock to 100 MHz and the burst to 32 bytes. The OTF writers starve during the LBO render and the heavy band glitches.
Keep that slow setting and move the LBO frames to HyperRAM. The render moves to the other channel and the glitches drop.
Switch commit mode to Synced. A late LBO render becomes a uniform stutter instead of seams.
Try RGB565 or a deeper line buffer, and turn on fixed 2× HyperRAM latency.

The model ignores the blit engine's own compute limits (blending, decompression), CPU traffic on SMIF, and exact arbitration. Latencies are typical values. Use it for direction and order of magnitude, then confirm on hardware with your datasheet values and the underrun interrupt enabled.